KE5BCCA1M KE5BCCA1M classification cam classification cam kawasaki lsi usa, inc. www.klsi.com silicon valley office: 2570 north first street, suite 301 eastern office: 501 edgewater dr., suite 510 san jose, ca 95131 wakefield, ma 01880 tel: (408) 570-0555 tel: (781) 224-4201 fax: (408) 570-0567 fax: (781) 224-2501 kawasaki lsi assumes no responsibility of liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special, or consequential damages. there are no warranties extended or granted by this document. the information herein is subject to change without notice from kawasaki lsi. v1.1 kawasaki lsi?s classification cam has a capacity of 1mbit (ternary) and 2 mbit (binary), and can be configured by bank in a mixture of binary and ternary modes. its primary application is in search and filtering. its flexibility, high speed, and high capacity make it appropriate for all layer 2/3/4 and above applications such as switches and routers in 10/100/1000 ethernet, terabit ethernet , oc-3/12 / 48 /192, t1/t3, frame relay, atm, xdsl and dwdm. this classification cam is also suitable for qos applications with its unique and patent-pending ? auto shift? commands. the search time is 15ns and the KE5BCCA1M is available in a 324-pin bga . features: high density: 2mbits binary, 1mbit for ternary organization: configurable table width; binary/ternary selected by bank binary case: 68-bit x 32k, 136-bit x 16k, 272-bit x 8k ternary case: 68-bit x 16k, 136-bit x 8k, 272-bit x 4k high speed search :15n sec (1 phase clock) latency: 30n sec (2 clock cycles) dual-port architecture: 68-bit i/o port with 1. 64-bit data bus (optional 32-bit configuration) 2. optional 4 extra bits on the data bus 3. 32-bit output port cascadable up to 32 pieces support for automatic data shifting continuous search during data shifting. multi-hit support (highest hit address output) 18 global mask registers (68-bit width) for data search/writing operation. automatic learning automatic storing of miss-hit data and time stamp of hit data synchronous operation clock rate: 66mhz (phase clock)/133mhz (operating clock) for synchronous operation 324-pin bga packaging 2.5v/3.3v power supply i/o port control pipeline execution control dat<63:0> oedatn datwdt rstn clk cntl<18:0> rwn cen cstn edat<3:0> phase extonn sad ead control and status register mask registers search logic control logic 136 bits x 8192 cam 136 bits x 8192 local mask priority encoder empty bit decoder phidn phodn pmin pmon flin flon shon smon phiun phoun flag logic oeodn od<31:0> output port control
KE5BCCA1M KE5BCCA1M classification cam classification cam kawasaki lsi usa, inc. www.klsi.com silicon valley office: 2570 north first street, suite 301 eastern office: 501 edgewater dr., suite 510 san jose, ca 95131 wakefield, ma 01880 tel: (408) 570-0555 tel: (781) 224-4201 fax: (408) 570-0567 fax: (781) 224-2501 kawasaki lsi assumes no responsibility of liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special, or consequential damages. there are no warranties extended or granted by this document. the information herein is subject to change without notice from kawasaki lsi. v1.1 timing chart of search operation (68bit) timing chart of read/write operation (68bit) cntl<1 8 :0> phase srch 0 srch 1 cen srch 2 srch 3 dat<63:0> rwn shon od<31:0> index 0 latency (2 phase ) latency (3 phase) hit0 t pd hit1 index 1 hit2 index 2 hit3 index 3 data0 data1 data2 data3 data0 data1 data2 data3 edat<3:0> <63:0> <63:0> <63:0> <63:0> <67:64> <67:64> <67:64> <67:64> mhit0 mhit1 mhit2 mhit3 latency (3 phase ) smon t pd t pd clk phase dat<63:0> write data0 write data1 latency (3 phase ) edat<3:0> write data0 write data1 latency (3 phase ) cntl<1 8 :0> reg1 reg0 reg1 cen rwn reg0 clk read data0 t pd read data1 read data0 t pd read data1
|
